13 Lecture Sections, 96 Labs

Verilog101^TM is a very comprehensive Verilog class that can serve as either a great way to get started for the Verilog newbie or as a reference for the seasoned Verilog designer. There are nearly 100 labs giving comprehensive "how to" examples of most Verilog language constructs. The class is also self-paced. All the work can be done independently by the engineer at his/her own computer and at his/her own pace.

There is no need to purchase your own Verilog simulator prior to starting this course. CBE has partnered with Aldec to bring you their easy-to-use Active-HDL suite of tools to use with the Verilog101^TM Labs. Click here to download your free copy of Active-HDL 7.2sp2.

The Verilog101^TM class is available on-line for a duration of 90 days upon registration. In that time you can access the class as often as needed and you will be able to download the lab database of 96 lab/examples for future use.

Verilog101^TM is recommended as a first course for a design or verification engineer wanting to expand their knowledge into the Verilog simulation world.

The students taking Verilog101^TM will be able to model and simulate various logic. A solid foundation is presented for both the design and verification engineer. The chapters included are:

 · Introduction  · Foundations  · Lab Key  · Getting Started  · Verilog Lexical Conventions  · Data Types  · Structural Modeling  · User Defined Primitives  · Behavioral Modeling  · Memories  · Operators  · Modeling Timing Delays and Timing Checks  · Synthesis Modeling

All CBE classes are self-paced. This schedule below is a suggestion based on a 90-day class.

All labs contain a working solution. Each quiz is self-grading.

A basic knowledge of boolean algebra and sequential logic design is recommended. This is a "foundations" class and can be taken as a first class in simulation or a first class in Verilog.

After becoming familiar with Verilog101^TM, the SystemVerilog101^TM (SV101^TM) class or SystemVerilog102^TM (SV102^TM) class should be taken.