Verilog101TM Class On-Line
13 Lecture Sections, 96 Labs
Verilog101TM is a very comprehensive Verilog class that can serve as either a great way to get started for the Verilog newbie or as a reference for the seasoned Verilog designer. There are nearly 100 labs giving comprehensive "how to" examples of most Verilog language constructs. The class is also self-paced. All the work can be done independently by the engineer at his/her own computer and at his/her own pace.
You must have access to a Verilog simulator to use the labs.
The Verilog101TM class is available on-line for a duration of 90 days upon registration. In that time you can access the class
as often as needed and you will be able to download the lab database of 96 lab/examples
for future use.
Verilog101TM is recommended as a first course for a design or verification engineer wanting to expand their knowledge into the Verilog simulation world.
The students taking Verilog101TM will be able to model and simulate various logic. A solid foundation is presented for both the design and verification engineer.
The chapters included are:
· Lab Key
· Getting Started
· Verilog Lexical Conventions
· Data Types
· Structural Modeling
· User Defined Primitives
· Behavioral Modeling
· Modeling Timing Delays and Timing Checks
· Synthesis Modeling
All CBE classes are self-paced. This schedule below is a suggestion based on a 90-day class.
All labs contain a working solution. Each quiz is self-grading.
|Time||Topics||Labs and Quizzes|
|Week 1||Introduction Foundations Getting Started||Lab 1|
|Week 2||Verilog Lexical Conventions||Labs 2-4, Quiz1|
|Week 3||Data Types||Labs 5-9, Quiz 2|
|Week 4||Structural Modeling||Labs 10-13, Quiz 3|
|Week 5||User Defined Primitives||Labs 14A-17B, Quiz 4|
|Week 6||Behavioral Modeling||Labs 18-38, Quiz 5|
|Week 7||Mid Class Review|| |
|Week 8||Memories||Labs 39-41, Quiz 6|
|Week 9||Operators||Labs 42-51, Quiz 7|
|Week 10||Modeling Timing Delays and Timing Checks||Labs 52A-57I, Quiz 8|
|Week 11||Synthesis Modeling||Labs 58-69, Quiz 9|
|Week 12||Review|| |
A basic knowledge of boolean algebra and sequential logic design is recommended. This is a "foundations" class and can be taken as a first class in simulation or a first class in Verilog.
After becoming familiar with Verilog101TM, the SystemVerilog101TM (SV101TM) class or SystemVerilog102TM (SV102TM) class should be taken.