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Verilog101TM Labs

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Verilog101TM Class On-Line

13 Lecture Sections, 96 Labs

Overview

Verilog101TM is a very comprehensive Verilog class that can serve as either a great way to get started for the Verilog newbie or as a reference for the seasoned Verilog designer. There are nearly 100 labs giving comprehensive "how to" examples of most Verilog language constructs. The class is also self-paced. All the work can be done independently by the engineer at his/her own computer and at his/her own pace.

You must have access to a Verilog simulator to use the labs.

The Verilog101TM class is available on-line for a duration of 90 days upon registration. In that time you can access the class as often as needed and you will be able to download the lab database of 96 lab/examples for future use.

Intended Audience

Verilog101TM is recommended as a first course for a design or verification engineer wanting to expand their knowledge into the Verilog simulation world.

Class Goals

The students taking Verilog101TM will be able to model and simulate various logic. A solid foundation is presented for both the design and verification engineer. The chapters included are:

 · Introduction  · Foundations  · Lab Key  · Getting Started  · Verilog Lexical Conventions  · Data Types  · Structural Modeling  · User Defined Primitives  · Behavioral Modeling  · Memories  · Operators  · Modeling Timing Delays and Timing Checks  · Synthesis Modeling

Schedule

All CBE classes are self-paced. This schedule below is a suggestion based on a 90-day class.

All labs contain a working solution. Each quiz is self-grading.

TimeTopicsLabs and Quizzes
Week 1Introduction Foundations Getting StartedLab 1
Week 2Verilog Lexical ConventionsLabs 2-4, Quiz1
Week 3Data TypesLabs 5-9, Quiz 2
Week 4Structural ModelingLabs 10-13, Quiz 3
Week 5User Defined PrimitivesLabs 14A-17B, Quiz 4
Week 6Behavioral ModelingLabs 18-38, Quiz 5
Week 7Mid Class Review 
Week 8MemoriesLabs 39-41, Quiz 6
Week 9OperatorsLabs 42-51, Quiz 7
Week 10Modeling Timing Delays and Timing ChecksLabs 52A-57I, Quiz 8
Week 11Synthesis ModelingLabs 58-69, Quiz 9
Week 12Review  


Prerequisites

A basic knowledge of boolean algebra and sequential logic design is recommended. This is a "foundations" class and can be taken as a first class in simulation or a first class in Verilog.

Course Progression

After becoming familiar with Verilog101TM, the SystemVerilog101TM (SV101TM) class or SystemVerilog102TM (SV102TM) class should be taken.

© 2006 Computer Based Education