9 Lecture Sections, 33 Labs

SystemVerilog - the ratified hardware description and verification language (HDVL) standard - is a major extension of the established IEEE 1364-2001 Verilog language, and was developed by Accellera to dramatically improve productivity in the design of large gate count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system level design flow.

CBE is a Catalyst partner of Synopsys Inc. CBE has two SystemVerilog classes, SystemVerilog101^TM and SystemVerilog102^TM. The first class, SystemVerilog101^TM, focuses on the design constructs in SystemVerilog. The second class SystemVerilog102^TM, focuses on the verification constructs of SystemVerilog. SystemVerilog101^TM has over 100 working lab/examples, all using new SystemVerilog constructs most useful in design. SystemVerilog102^TM has over 30 working lab/examples, using the SystemVerilog constructs geared toward verification.

The SystemVerilog102^TM class is available on-line for a duration of 90 days upon registration. The labs are yours to download and keep. Unlike Verilog101^TM, SystemVerilog101^TM and SystemVerilog102^TM comes with no simulator. You must have access to a SystemVerilog simulator.

SystemVerilog102^TM contains the constructs of SystemVerilog most often used by the verification engineer. The topics covered are needed by the design engineer as well however and the class is ideal for anyone needing to expand their knowledge into SystemVerilog.

The SystemVerilog102^TM class contains:

 · Immediate Assertion  · Concurrent Assertions  · Verification Flow Overview  · Scheduling  · Referencing a Sequence  · Formal Arguments- Sequence  · Concatenation  · Clock Range  · Extending a Sequence  · Consecutive Repetition  · Infinite Repetition  · Goto Repetition  · Non-consecutive Repetition  · Anding  · Intersecting  · Oring  · Throughout  · Within  · $rose  · $fell  · $stable  · First Match  · Ended  · Triggered  · Formal Argument-Property  · Overlapping Implication  · Non-overlapping Implication  · Inverting a Property  · $past  · disable iff  · Action Blocks  · Severity-$fatal  · $warning  · $error  · $info  · Cover  · Binding

All CBE classes are self-paced. This schedule below is a suggestion based on a 90-day class. All labs contain a working solution. Each quiz is self-grading.

There is an assumption that the student knows basic Verilog. Verilog101^TM is the perfect choice to fulfill this requirement.

After taking SystemVerilog101^TM (SV101^TM), SystemVerilog102^TM (SV102^TM) should be taken. The information in SV102^TM is a perfect follow-on to SV101^TM.