11 Lecture Sections, 106 Labs

SystemVerilog - the ratified hardware description and verification language (HDVL) standard - is a major extension of the established IEEE 1364-2001 Verilog language, and was developed by Accellera to dramatically improve productivity in the design of large gate count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system level design flow.

ComputerBasedEducation (CBE) is a Catalyst partner of Synopsys Inc. CBE has two SystemVerilog classes currently available. The first class, SystemVerilog101^TM, focuses on the design constructs in SystemVerilog. The second class SystemVerilog102^TM, focuses on the verification constructs of SystemVerilog. The design oriented class (SystemVerilog101^TM) has over 100 working lab/examples, all using new SystemVerilog constructs.

The SystemVerilog101^TM class is available on-line for a duration of 90 days upon registration. The labs are yours to download and keep. Unlike Verilog101^TM, SystemVerilog101^TM comes with no simulator. You must have access to a SystemVerilog simulator.

SystemVerilog101^TM contains the constructs of SystemVerilog most often used by the design engineer. The topics covered are needed by the verification engineer as well however and the class is ideal for anyone needing to expand their knowledge into SystemVerilog.

The SystemVerilog101^TM class contains:

 · New Procedural Blocks  · Data Types  · Hierarchy  · Structures  · Unions  · Arrays  · New SystemVerilog Operators  · Functions in SystemVerilog  · Tasks in SystemVerilog  · Interface  · case and if statements  · Review and Miscellaneous Labs

All CBE classes are self-paced. This schedule below is a suggestion based on a 90-day class. All labs contain a working solution. Each quiz is self-grading.

There is an assumption that the student knows basic Verilog. Verilog101^TM is the perfect choice to fulfill this requirement.

After taking SystemVerilog101^TM (SV101^TM), SystemVerilog102^TM (SV102^TM) should be taken. The information in SV102^TM is a perfect follow-on to SV101^TM.