For use with our SV101, SV102 (SystemVerilog) classes.

Riviera-PRO Overview

Riviera-PRO is a high-performance verification platform forASIC and FPGA design teams, equipped with mixed-language simulation engine and advanced debugging tools. Riviera-PRO supports Electronic System Level (ESL) Verification with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Linting. Riviera-PRO works in command line mode for maximum speed and is also equipped with a powerful GUI for enhanced editing, tracing, and debugging. Riviera-PRO is compatible with popular EDA products such as Synopsys® SmartModels™, Novas™, Denali®, MATLAB® and Simulink®.

Top features:

• Common-Kernel VHDL, Verilog, SystemVerilog, SystemC/C/C++, EDIF Simulator
• 64-Bit Multi-Threaded Design Environment
• Script compatible with other HDL simulators
• Unified HDL/SystemC code level Debugging & Post Simulation Debugging
• Accelerated Waveform Viewer and Code Coverage
• SystemVerilog, PSL and OVA Assertions and Functional Coverage
• VHDL and Verilog Code Linting
• DSP algorithm design/co verification with MATLAB® and Simulink®
• Multi-Platform (32/64bit Linux®, Windows®)

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